memory controller
英 [ˈmeməri kənˈtrəʊlə(r)]
美 [ˈmeməri kənˈtroʊlər]
网络 显存控制器; 内存控制器; 存储控制器; 存储器控制器; 记忆体控制器
双语例句
- On-chip L3 directory and memory controller
芯片上L3目录和内存控制器 - A memory controller on the chip
芯片上集成内存控制器 - Technologies, Types of RAM and ROM, Memory Controller Circuits, Specialty Memories, High-performance Interfaces.
RAM和ROM的技术和类型，存储器控制电路，特殊存储器，高性能接口。 - A memory controller in an SOC was designed based on the project of SOC used in network and communication.
以一个应用于网络与通讯领域的SOC芯片研发项目为背景，设计了SOC芯片上的存储控制器。 - The new memory controller is designed with three interfaces: memory interface, MPU/ MCU interface and USB interface.
新型存储控制器设计了3类接口：存储器接口、MPU/MCU接口、USB接口。 - Performance Evaluation and Optimization of On-chip Memory Controller
片上内存控制器性能评估和优化 - Memory Controller Design of System-on-a-Chip
系统芯片中的存储器接口电路设计 - A memory controller is designed to stabilize the given system.
设计了一个有记忆型控制器。 - This paper analyzes the whole functions and separate modules of memory controller and interrupt controller and introduces the normal IP design flow.
本文详细分析了内存控制器和中断控制器的总体功能以及内部各个模块的划分，介绍了一般IP设计流程。 - Firstly, TS-1 memory system architecture is introduced. Then some of the critical issue during the process of design and implementation are covered, including the design of Cache system and memory controller.
介绍了TS-1存储系统的体系结构，针对设计和实现过程中的关键问题进行了讨论，包括Cache系统的设计和存储控制器的设计。 - This memory controller can provide interfaces to several types of SRAM, FLASH and I/ O. It has been applied and verified in a embedded system.
此存储器控制器可提供60x总线与多种类型的SRAM的接口，及与FLASH和I/O的接口，已在嵌入式系统的设计中得到了应用和验证。 - The design of a FIFO memory controller was completed with VHDL.
介绍了用VHDL实现FIFO存储控制器的设计，给出了整个FIFO系统的控制原理，对控制单元作了详细的说明，并给出控制器的读、写时序图、写周期的状态图和部分编制的程序。 - Memory controller design and IP interconnection are the common issues in System-on-a-Chip ( SoC) design.
存储器控制电路的设计和IP互连是SoC设计中常遇到的问题。 - As a part of the Embedded System Development Platform project, this task focuses on the design and implementation of FPGA-based multi-port memory controller, providing a new approach for circuit designs which need mass storage.
本课题以嵌入式系统开发平台科研项目为背景，重点研究了基于FPGA的多端口存储控制器的设计与实现技术，为需要大容量存储器的系统设计提供了新思路。 - By using hardware/ software co-design platform-based SOC design method, a Mass-Storage memory controller SOC design platform is built.
基于硬件和软件协同仿真平台的SOC全新的设计方法，创建了本文所研究的大容量存储（Mass-Storage）控制SOC芯片的硬件和软件协同仿真平台。 - A Programmable Embedded Asynchronous SRAM Memory Controller
一种可编程嵌入式异步SRAM存储控制器 - Although different SoC platform will have different modules, there are some necessary modules, such as memory controller and interrupt controller.
不同的SoC平台中，可能包含的模块各不相同。但是内存控制器和中断控制器是必不可少的。 - In this paper, a new technology, which is realized by a VPFB in memory controller design, is presented, and its efficiency is analyzed by simulation.
本文提出了一种硬件预取方法，即在存储控制器中设计一个VPFB机构用来隐藏访存延迟，并通过模拟分析了它的效果。 - Study on Technology of Error Control of Memory Controller
内存控制器的差错控制技术研究 - The embedded hyperthermia instrument consists of inner-tissue temperature acquisition and conversion system, ultrasound power controlling signal generation module, memory controller, human-machine intercommunication system ( including LCD display and keyboard input) and other basic function modules.
嵌入式肿瘤热疗系统包括组织温度采集与转换系统、超声功率控制信号发生模块、存储管理系统、人机交互系统（包括液晶显示及键盘输入）以及其他基本功能模块。 - MPU/ MCU interface could control memory interface and the state of the new memory controller.
MPU/MCU接口可以控制存储器接口和存储控制器的状态； - Arbitration and control module is the main part of the top module used to implement the state machine and system timing control. Parameter table module is the SDRAM memory controller interface for reading parameter information when image processing.
仲裁与控制模块是顶模块的主体部分，主要实现系统状态机和时序控制；参数表模块主要实现SDRAM存储器的控制器接口，用于图像处理时读取参数信息。 - In Sec-tion 4.2, we design a memory controller for T-S fuzzy discrete-time systems with random input delay.
在4.2节，对一类带有随机输入时滞的T-S模糊离散系统设计了有记忆控制器。 - The structure of the general-purpose memory controller divided in terms of clock generation module, control module, command module, instruction decoding module and data path module, as well as the analysis and design for the structure and implementation of each module. 3.
各内存控制器的结构划分：由时钟产生模块、控制命令模块、指令译码模块和数据通道模块组成，对各模块的结构及实现方法进行了分析和设计。 - Therefore, memory controller determines memory performance or even the overall system performance.
因此，内存控制器便成为影响内存性能发挥乃至计算机系统整体性能提升的关键因素之一。 - Considering the needs of system integration, the flash memory controller is packaged as IP Core, which accords with the processor local bus interface standard.
考虑到系统集成的需要，将实现的闪存控制器封装成符合处理器本地总线（ProcessorLocalBus，PLB）接口标准的IP核，并根据IP核实现底层驱动程序。 - For memory controller optimization, we focus on memory request scheduling algorithm.
存储控制器方面，本文主要研究访存请求调度算法优化。 - Based on the new built model, memory controller is designed and sufficient conditions for the stochastic mean square stable of T-S fuzzy discrete-time systems are obtained by using Lyapunov functional method.
在新建模型的基础上，通过利用Lyapunov泛函稳定性理论，设计了目标系统的有记忆的控制器，并且得到了该类T-S模糊离散系统随机均方稳定的充分性条件。 - Some important parameters such as data depth, data width, maximum capacity, memory type, and bank quantity of the memory chip are decided by memory controller which automatically operates the memory access requests from CPU.
内存控制器决定着计算机系统内存的最大容量、BANK数量、类型、速度、颗粒数据深度和数据宽度等重要参数，并以自动化的方式处理CPU对存储器的访问请求。 - In computer systems, memory controller is one of the most important control components for data exchange between CPU and memory.
内存控制器是影响计算机系统内存与CPU之间数据交换的重要部件之一。